1. Field of the Invention
The present invention relates to a timing library test apparatus, a method for testing a timing library, and a computer readable medium comprising a timing library test program, and more particularly, to a timing library test apparatus, a method for testing a timing library, and a computer readable medium comprising a timing library test program that are used for verifying the timing library of a semiconductor integrated circuit.
2. Related Art
To create a timing library (such as a timing library for input timings of a sequential circuit) of an ordinary semiconductor integrated circuit, the input timings of the sequential circuit are measured in the vicinity of a meta-stable area in which the semiconductor integrated circuit operates in a very unstable manner. In this meta-stable area, it is difficult to obtain a stable output waveform. The output waveform tends to have an insufficient transition accompanied by oscillations or a hazard. This becomes even more prominent particularly where the source voltage of the semiconductor integrated circuit becomes lower.
However, in creating the timing library, even if the output waveform has the insufficient transition, it is determined that the semiconductor integrated circuit correctly operates as long as the output waveform is higher than a reference voltage that is a logical threshold value. In such a case, a logic gate having this output waveform cannot correctly operate if the output waveform is input. Therefore, even if the output waveform is higher than the reference voltage, it should be determined that the semiconductor integrated circuit can not correctly operate. However, in practice, it is determined that the semiconductor integrated circuit can correctly operate, and the timing of an input waveform at that point is registered as a hold time or a setup time in the timing library. Since the semiconductor integrated circuit can not correctly operate in accordance with the registered hold time or setup time, the registered hold time or setup time is a singular point in the timing library. As a result, a user cannot read accurate input timings from the timing library including the singular point. In this manner, in the conventional creation of the timing library, an incomplete timing library might be formed.
Furthermore, after the timing library is created, it is required that the user tests whether the timing library is incomplete (that is, whether the timing library includes the singular point) in a visual test.
However, such a visual test is very difficult, since enormous amounts of data are registered in the timing library. Therefore, if the user overlooks the singular point in the visual test, the user would verify the input timings of the sequential circuit with the use of the incomplete timing library. As a result, although the input timings of the sequential circuit have a failure, such a failure is overlooked. Thereby, a malfunction of the semiconductor integrated circuit, and increases in circuit size and power consumption due to an additional timing adjustment circuit for setting excess constraints (hereinafter referred to as “timing constraints”) on the input timings of cells in the semiconductor integrated circuit are caused.
Although various solutions to problems in the creation of the timing library have been suggested (see JP-A No. 09-305650 (Kokai)), no solutions to these problems (the malfunction of the semiconductor integrated circuit and the increases in circuit size and power consumption) have been suggested.